The manufacturing of integrated circuits typically includes multiple photolithography processes. When the dimensions of the integrated circuits become increasingly smaller, the requirement for controlling the critical dimensions of the integrated circuits is also increasingly tightened. The critical dimensions are the minimum width of gate electrodes of the transistors in the wafer. The critical dimensions may be used as a reference for forming metal layers.
In conventional processes for controlling the critical dimensions (which is essentially controlling the sizes of the formed features), a photo resist is applied on a wafer. The photo resist is exposed using a photolithography mask, which includes opaque patterns and transparent patterns. The photo resist is then patterned through development. The patterned photo resist is then used to etch an underlying hard mask. The wafer is then sent to a metrology tool, which measures the sizes of the patterns in the hard mask. The measured sizes are compared to the specified ranges, which specify the desirable ranges of features to be formed. Hence, it can be determined whether the measured sizes are greater than, smaller than, or equal to, the specified ranges. The determined information is then feedback to the etching of the hard mask in the next wafer in order to adjust the sizes of the features in the next wafer.